发表论文
[1]Yanxia Wu,Ye Yuan,Jian Guan,Libo Yin,Jinyong Chen,Ge Zhang,Pengming Feng.Joint Convolutiona Neural Network for Small-scale Ship Classification in SAR Images[C].2019 IEEE International Geoscience and Remote Sensing Symposium (IGARSS),2019:2619-2622
[2]吴艳霞,梁楷,刘颖,崔慧敏.深度学习FPGA加速器的进展与趋势[J/OL].计算机学报,2019:1-20
[3]张国印,王泽宇,吴艳霞,布树辉.面向场景解析的空间结构化编码深度网络[J].哈尔滨工程大学学报,2017,38(12):1928-1936.(EI:20181304954988)
[4]ZeYu Wang, YanXia Wu, ShuHui Bu, PengCheng Han, GuoYin Zhang.Structural inference embedded adversarial networks for scene parsing,PloS one 2018, 13(4): e0195114. ( SCI: 000429791900025 2.806)
[5]王泽宇,吴艳霞,张国印,布树辉. 基于空间结构化推理深度融合网络的RGB-D场景解析,电子学报 2018, 46(5): 1253-1258. ( EI: 20183905879719)
[6]XingMei Wang,GuoQiang Wang,YanXia Wu.An Adaptive Particle Swarm Optimization for Underwater Target Tracking in Forward Looking Sonar Image Sequences,IEEE Access 2018(6): 46833-46843(SCI:000445146100001)
[7]刘书勇,林俊宇,吴艳霞,张博为.基于矩阵三角化分解的Cholesky分解及FPGA并行结构设计[J].清华大学学报(自然科学版),2016,56(09):963-968.(EI:20163902858112)
[8]郭振华,吴艳霞,张国印,戴葵. 面向类仿射型数组下标应用的参数化并行存储结构模板, 电子学报 2016.8(44): 1956-1961. (EI:20163402737344)
[9]郭振华,吴艳霞,张国印,戴葵. 面向ASCRA的循环流水启动间距自动分析及优化, 计算机学报,2015
[10]刘书勇,吴艳霞,张博为,张国印,戴葵. 基于可重构计算系统的矩阵三角化分解硬件并行结构研究, 电子学报,2014
[11]郭振华, 吴艳霞*, 张国印, 戴葵, 面向 ASCRA 的循环流水启动间距自动分析及优化,2014 年全国高性能计算学术年会会议论文集 (CCF HPC China 2014) ,广州, 2014.11.6-8:47-56.
[12]牛晓霞, 吴艳霞*, 朱若平, 顾国昌等. 基于多种硬件实现方式探索的软硬件划分算法,吉林大学学报(工学版), 2014, 4(44): 1088-1097. (EI: 20142917960629).
[13]刘书勇, 林俊宇, 吴艳霞等. 基于子矩阵更新同一化并行算法的 FPGA 矩阵计算并行结构设计研究, 2014 中国计算机应用大会录用(推荐到清华大学学报发表).
[14]李静梅, 王雪, 吴艳霞, 一种改进的优先级列表任务调度算法, 计算机科学, 2014,41(5):20-23.
[15]李静梅, 张大虎, 吴艳霞, 孙传恒, 基于蚁群优化算法的异构多核线程调度方法, 计算机工程与设计, 2014, 35(6):1946-1950.
[16]Zhenhua Guo, Yanxia Wu*, Guoyin Zhang, Tianxiang Sui, An improved FPGAs-based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler, 10th International Symposium Advanced Parallel Processing Technologies (APPT 2013), LNCS 8299, pp.307-318. Stockholm, Sweden, August 2013. (EI: 20140517259439)
[17]Zhijian Lu, Yanxia Wu*, GuochangGu, Jingmei Li, Automatic Mapping of Nested Non-counting Loop onto FPGAs, Journal of Digital Content Technology and its Applications, 2013, 7(1):421-429. (EI:20130415927616)
[18]郭振华, 吴艳霞*, 张国印, 杨杰,顾国昌, 面向 C2VHDL 编译器的基本块级指针分析算法, 吉林大学学报(工学版), 2013, 43(2): 417-423.(EI: 20131316153693)
[19]郭振华;吴艳霞;张国印;杨杰;顾国昌. 面向C2VHDL编译器的基本块级指针分析算法,吉林大学学报(工学版),2013
[20]Niu Xiaoxia, Wu Yanxia*, Zhang Bowei, Gu Guochang, Zhang Guoyin, Rapid FPGA-based delay estimation for the hardware/software partitioning, Journal of Networks, 2013, 8(5):1183-1190. ( EI: 20132316405504)
[21]Zhijian Lu, Yanxia Wu*, Zhenhua Guo, Guochang Gu, A Rotation-based Data Buffering Architecture for Convolution Filtering in a Field Programmable Gate Array, Journal of Computers. 2013, 8(6):1411-1416. (EI: 20132216371523)
[22]Wu Yanxia, Gu Guochang, Sun Yanteng, YangMin, Yang Jie, Niu Xiaoxia, Sun Lin, ASCRA:Application-Specific Compiler for Reconfigurable Architecture, 计算机科学与探索(中国计算机学会 2010 未来计算大会(CCF CFC'2010)录用), 2011, 5(3): 267-279.
[23]Niu Xiaoxia, Wu Yanxia*, Zhang Bowei, Gu Guochang, Zhang Guoyin, Auto Estimation Model of FPGA based Delay for the Hardware/Software Partitioning, Journal of Computational Information Systems, 2013, 9(17): 6767-6774. ( EI:20134416914545)
[24]Niu Xiaoxia, Wu Yanxia*, Zhang Bowei, Gu Guochang, Zhang Guoyin, Improved FPGA-Based Area Estimation Method for Hardware/Software Partitioning, Journal of Convergence Information Technology, 2013, 8(4): 636-643.
[25]Zhijian Lu, Yanxia Wu*, Guochang Gu, A Computation and Storage Trade-Off in Mapping 2-D Convolution Networks on Field Programmable Gate Arrays, ICIC Express Letters, 2013, 7(8):2361-2367. (EI: 20132116352544)
[26]李静梅, 金胜男, 基于异构多核处理器的静态任务调度研究, 计算机工程与设计, 2013,34(1): 178-184.
[27]陆志坚, 吴艳霞*, 郭振华, 顾国昌, 基于脉动阵列的 HMMer 加速系统, 计算机工程与应用, 2013, 49(8):76-80.
[28]张博为, 吴艳霞*, 孙霖, 顾国昌, 一种快速求解二值线性方程组的并行结构, 计算机工程. 2012, 38(11):281-286.
[29]Sun Lin, Wu Yanxia*, Zhang Bowei, Gu Guochang, RAM Access Optimization Strategy Oriented to Reconfigurable Compiling Technique, International Journal of Advancements in Computing Technology, 2012, 4(20): 479-486. (EI: 20124715701811)
[30]Zhijian Lu, Yanxia Wu*, Zhenhua Guo, Guochang Gu, Scheduling Algorithms for Compiler of Loop Pipelining Designs on FPGAs, International Journal of Advancements in Computing Technology, 2012, 4(23):67-78. (EI:20130215887986)
[31]牛晓霞, 吴艳霞*, 顾国昌, 张博为, 李静梅, 基于edge profiling的循环运行时信息分析方法, 计算机工程与应用, 2012, 48(29): 8-12.
[32]郭振华, 吴艳霞*, 张国印, 陆志坚, 牛晓霞, 一种改进 ASAP 调度的流水线自动划分算法, 计算机科学(计算机体系结构学术年会(ACA 2012)录用), 2012, Vol.39(11):89-93.
[33]杨敏, 吴艳霞*, 顾国昌, 孙延腾, 面向可重构编译技术的 RAM 访问优化算法, 计算机工程, 2011, 37(2):284-289.
[34]Wu Yanxia, Gu Guochang, Sun Yanteng, Yang Min, Yang Jie, Niu Xiaoxia, Sun Lin. ASCRA: Application-Specific Compiler for Reconfigurable Architecture, 计算机科学与探索,2011
[35]吴艳霞,顾国昌,戴葵,刘海波,沈晶.汇编级软硬结合的控制流检测方法, 计算机研究与发展,2010
[36]吴艳霞,顾国昌,戴葵,沈晶,刘海波.基于签名的控制流错误检测算法检测能力的验证模型, 宇航学报,2010